TY - CHAP
T1 - A stimulator ASIC with capability of neural recording during inter-phase delay
AU - Liu, Xiao
AU - Demosthenous, Andreas
AU - Jiang, Dai
AU - Vanhoestenberghe, Anne
AU - Donaldson, Nick
PY - 2011
Y1 - 2011
N2 - This paper presents a single chip solution for a combined stimulation and recording system for functional electrical stimulation applications. The on-chip recording amplifier blanks large stimulation artifacts occurring in the cathodic (i.e., stimulation) and anodic (i.e., recuperation) phases of a stimulation pulse. By making the stimulator output stage float and recording during the delay between cathodic and anodic impulses, the recording start time can be greatly advanced from the end of a complete stimulation cycle to the end of the cathodic phase. The ASIC was fabricated in a 0.6 μm HV CMOS technology, occupies a core area of 5.3 mm2 and operates from a single 18 V power supply. It has 5 I/O pads for power and data communication and another 5 I/O pads for connecting to the electrodes. The operation of the ASIC has been verified both in-vitro and in-vivo.
AB - This paper presents a single chip solution for a combined stimulation and recording system for functional electrical stimulation applications. The on-chip recording amplifier blanks large stimulation artifacts occurring in the cathodic (i.e., stimulation) and anodic (i.e., recuperation) phases of a stimulation pulse. By making the stimulator output stage float and recording during the delay between cathodic and anodic impulses, the recording start time can be greatly advanced from the end of a complete stimulation cycle to the end of the cathodic phase. The ASIC was fabricated in a 0.6 μm HV CMOS technology, occupies a core area of 5.3 mm2 and operates from a single 18 V power supply. It has 5 I/O pads for power and data communication and another 5 I/O pads for connecting to the electrodes. The operation of the ASIC has been verified both in-vitro and in-vivo.
UR - http://www.scopus.com/inward/record.url?scp=82955201668&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2011.6044903
DO - 10.1109/ESSCIRC.2011.6044903
M3 - Conference paper
AN - SCOPUS:82955201668
SN - 9781457707018
T3 - European Solid-State Circuits Conference
SP - 215
EP - 218
BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
T2 - 37th European Solid-State Circuits Conference, ESSCIRC 2011
Y2 - 12 September 2011 through 16 September 2011
ER -