A Sub-nW/kHz Relaxation Oscillator with Ratioed Reference and Sub-Clock Power Gated Comparator

TY - JOUR

T1 - A Sub-nW/kHz Relaxation Oscillator with Ratioed Reference and Sub-Clock Power Gated Comparator

AU - Savanth, A.

AU - Weddell, A.S.

AU - Myers, James

AU - Flynn, D.

AU - Al-Hashimi, Bashir M.

N1 - cited By 0

PY - 2019/11

Y1 - 2019/11

N2 - Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz-a 4× improvement over state-of-the-art for comparable stability.

AB - Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz-a 4× improvement over state-of-the-art for comparable stability.

U2 - 10.1109/JSSC.2019.2930360

DO - 10.1109/JSSC.2019.2930360

M3 - Article

VL - 54

SP - 3097

EP - 3106

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 11

ER -