Aging Benefits in Nanometer CMOS Designs

Daniele Rossi; Vasileios Tenentes; Sheng Yang; Saqib Khursheed; Bashir M. Al-Hashimi

doi:10.1109/TCSII.2016.2561206

Aging Benefits in Nanometer CMOS Designs

Daniele Rossi, Vasileios Tenentes, Sheng Yang, Saqib Khursheed, Bashir M. Al-Hashimi

Engineering

Research output: Contribution to journal › Article › peer-review

37 Citations (Scopus)

Abstract

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.

Original language	English
Article number	7463508
Pages (from-to)	324-328
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	3
Early online date	3 Mar 2016
DOIs	https://doi.org/10.1109/TCSII.2016.2561206
Publication status	Published - 2 May 2016

Keywords

Bias temperature instability (BTI) aging
energy efficiency
leakage current
nanometer technology
static power

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2016.2561206

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AU - Rossi, Daniele

AU - Tenentes, Vasileios

AU - Yang, Sheng

AU - Khursheed, Saqib

AU - Al-Hashimi, Bashir M.

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AB - In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.

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Aging Benefits in Nanometer CMOS Designs

Abstract

Keywords

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