FPGA Applied to Latency Reduction for the Tactile Internet

TY - JOUR

T1 - FPGA Applied to Latency Reduction for the Tactile Internet

AU - Junior, José C.V.S.

AU - Silva, Sérgio N.

AU - Torquato, Matheus F.

AU - Mahmoodi, Toktam

AU - Dohler, Mischa

AU - Fernandes, Marcelo A.C.

PY - 2022/10/16

Y1 - 2022/10/16

N2 - Tactile internet applications allow robotic devices to be remotely controlled over a communication medium with an unnoticeable time delay. In bilateral communication, the acceptable round trip latency is usually 1 ms up to 10 ms, depending on the application requirements. The communication network is estimated to generate 70% of the total latency, and master and slave devices produce the remaining 30%. Thus, this paper proposes a strategy to reduce 30% of the total latency produced by such devices. The strategy is to use FPGAs to minimize the execution time of device-associated algorithms. With this in mind, this work presents a new hardware reference model for modules that implement nonlinear positioning and force calculations and a tactile system formed by two robotic manipulators. In addition to presenting the implementation details, simulations and experimental tests are performed in order to validate the hardware proposed model. Results associated with the FPGA sampling rate, throughput, latency, and post-synthesis occupancy area are analyzed.

AB - Tactile internet applications allow robotic devices to be remotely controlled over a communication medium with an unnoticeable time delay. In bilateral communication, the acceptable round trip latency is usually 1 ms up to 10 ms, depending on the application requirements. The communication network is estimated to generate 70% of the total latency, and master and slave devices produce the remaining 30%. Thus, this paper proposes a strategy to reduce 30% of the total latency produced by such devices. The strategy is to use FPGAs to minimize the execution time of device-associated algorithms. With this in mind, this work presents a new hardware reference model for modules that implement nonlinear positioning and force calculations and a tactile system formed by two robotic manipulators. In addition to presenting the implementation details, simulations and experimental tests are performed in order to validate the hardware proposed model. Results associated with the FPGA sampling rate, throughput, latency, and post-synthesis occupancy area are analyzed.

KW - FPGA

KW - haptic devices

KW - latency reduction

KW - tactile internet

UR - http://www.scopus.com/inward/record.url?scp=85140933360&partnerID=8YFLogxK

U2 - 10.3390/s22207851

DO - 10.3390/s22207851

M3 - Article

C2 - 36298203

AN - SCOPUS:85140933360

SN - 1424-8220

VL - 22

JO - Sensors (Basel, Switzerland)

JF - Sensors (Basel, Switzerland)

IS - 20

M1 - 7851

ER -