Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays

TY - JOUR

T1 - Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays

AU - Kulkarni, Shruti R.

AU - Kadetotad, Deepak Vinayak

AU - Yin, Shihui

AU - Seo, Jae Sun

AU - Rajendran, Bipin

PY - 2019/11

Y1 - 2019/11

N2 - In this paper, we propose a Spin Transfer Torque RAM (STT-RAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the time-based signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of non-volatile STT-RAMs, read/write peripheral circuits, and digital logic for the spiking neurons. Inter-core communication is realized through on-chip routing network by sending/receiving spike packets. Unlike prior works that use multi-level states of non-volatile memory (NVM) devices for the synaptic weights, we use the technologically-mature STT-RAM devices for binary data storage. The design studies are conducted using a compact model for STT-RAM devices, tuned to capture the state-of-the-art experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STT-RAM based neurosynaptic core designed in 28 nm technology node has approximately 6× higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves ∼ 2× higher performance per Watt compared to other memristive neural network accelerator designs in the literature.

AB - In this paper, we propose a Spin Transfer Torque RAM (STT-RAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the time-based signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of non-volatile STT-RAMs, read/write peripheral circuits, and digital logic for the spiking neurons. Inter-core communication is realized through on-chip routing network by sending/receiving spike packets. Unlike prior works that use multi-level states of non-volatile memory (NVM) devices for the synaptic weights, we use the technologically-mature STT-RAM devices for binary data storage. The design studies are conducted using a compact model for STT-RAM devices, tuned to capture the state-of-the-art experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STT-RAM based neurosynaptic core designed in 28 nm technology node has approximately 6× higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves ∼ 2× higher performance per Watt compared to other memristive neural network accelerator designs in the literature.

KW - Crossbar arrays

KW - Neuromorphic hardware

KW - Non-volatile memories

KW - Spiking neural networks

KW - STT-RAM

UR - http://www.scopus.com/inward/record.url?scp=85079196851&partnerID=8YFLogxK

U2 - 10.1109/ICECS46596.2019.8964886

DO - 10.1109/ICECS46596.2019.8964886

M3 - Conference paper

SP - 438

EP - 441

JO - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

JF - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Y2 - 27 November 2019 through 29 November 2019

ER -