Robust Digital Correction of Analog Errors in Cascaded Sigma Delta

TY - JOUR

T1 - Robust Digital Correction of Analog Errors in Cascaded Sigma Delta

AU - Gani, Mahbub

PY - 2005/6

Y1 - 2005/6

N2 - Cascaded sigma-delta converters relax the requirements on the oversampling ratio for a given resolution. However, their performance is sensitive to mismatches in the analog components. Previous work has explored adaptive calibration schemes to address the mismatch problem, but such methods lead to an increase in the implementation complexity. In the present work an alternative strategy to the adaptive one is pursued in which robust digital correction filters are synthesized. The main contributions reported in this paper are the development and validation of the synthesis framework and some solutions to the synthesis problem. Specifically, a robust correction filter is synthesised for the 2-1 cascaded architecture, which exhibits lower variation in the signal-to-noise and distortion ratio over the nominal correction filter. Since the filters are fixed at the design stage, the proposed scheme does not add an additional burden on the implementation. © 2005 Elsevier Ltd. All rights reserved

AB - Cascaded sigma-delta converters relax the requirements on the oversampling ratio for a given resolution. However, their performance is sensitive to mismatches in the analog components. Previous work has explored adaptive calibration schemes to address the mismatch problem, but such methods lead to an increase in the implementation complexity. In the present work an alternative strategy to the adaptive one is pursued in which robust digital correction filters are synthesized. The main contributions reported in this paper are the development and validation of the synthesis framework and some solutions to the synthesis problem. Specifically, a robust correction filter is synthesised for the 2-1 cascaded architecture, which exhibits lower variation in the signal-to-noise and distortion ratio over the nominal correction filter. Since the filters are fixed at the design stage, the proposed scheme does not add an additional burden on the implementation. © 2005 Elsevier Ltd. All rights reserved

U2 - 10.1016/j.measurement.2005.03.003

DO - 10.1016/j.measurement.2005.03.003

M3 - Article

VL - 37

SP - 310

EP - 319

JO - Measurement

JF - Measurement

IS - 4

ER -